Multi-objective Digital VLSI Design Optimisation

Modern VLSI design's complexity and density has been exponentially increasing over the past 50 years and recently reached a stage within its development, allowing heterogeneous, many-core systems and numerous functions to be integrated into a tiny silicon die. These advancements have revealed intrinsic physical limits of process technologies in advanced silicon technology nodes. Designers and EDA vendors have to handle these challenges which may otherwise result in inferior design quality, even failures, and lower design yields under time-to-market pressure. Multiple or many design objectives and constraints are emerging during the design process and often need to be dealt with simultaneously. Multi-objective evolutionary algorithms show flexible capabilities in maintaining multiple variable components and factors in uncertain environments. The VLSI design process involves a large number of available parameters both from designs and EDA tools. This provides many potential optimisation avenues where evolutionary algorithms can excel. This PhD work investigates the application of evolutionary techniques for digital VLSI design optimisation. Automated multi-objective optimisation frameworks, compatible with industrial design flows and foundry technologies, are proposed to improve solution performance, expand feasible design space, and handle complex physical floorplan constraints through tuning designs at gate-level. Methodologies for enriching standard cell libraries regarding drive strength are also introduced to cooperate with multi-objective optimisation frameworks, e.g., subsequent hill-climbing, providing a richer pool of solutions optimised for different trade-offs. The experiments of this thesis demonstrate that multi-objective evolutionary algorithms, derived from biological inspirations, can assist the digital VLSI design process, in an industrial design context, to more efficiently search for well-balanced trade-off solutions as well as optimised design space coverage. The expanded drive granularity of standard cells can push the performance of silicon technologies with offering improved solutions regarding critical objectives. The achieved optimisation results can better deliver trade-off solutions regarding power, performance and area metrics than using standard EDA tools alone. This has been not only shown for a single circuit solution but also covered the entire standard-tool-produced design space

Multi-objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Abstract Modern electronic design automation (EDA) tools can handle the complexity of state‐of‐the‐art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independently optimised design step, overheads and inefficiencies can accumulate in the resulting overall design. Performing design‐specific optimisation from a more global viewpoint requires more time due to the larger search space but has the potential to provide solutions with improved performanc. In this work, a fully‐automated, multi‐objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, prior to physical implementation, through MO population‐based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is aimed at digital circuit optimisation at the block level, where it is capable of expanding the design space and offers a set of trade‐off solutions for different case‐specific utilisation. We have applied the proposed multi‐objective electronic design automation flow (MOEDA) framework to ISCAS‐85 and EPFL benchmark circuits by using a commercial 65 nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow and how simultaneously a significant improvement in PPA metrics is achieved

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

Modern electronic design automation (EDA) tools can handle the complexity of state-of-the-art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independent-optimised design step, overhead and inefficiency can accumulate in the resulting overall design. Performing design-specific optimisation from a more global viewpoint requires more time due to the larger search space, but has the potential to provide solutions with improved performance. In this work, a fully-automated, multi-objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, preceding physical implementation, through multi-objective population-based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is aimed at digital circuit optimisation at the block-level, where it is capable of expanding the design space and offers a set of trade-off solutions for different case-specific utilisation. We have applied the proposed MOEDA framework to ISCAS-85 and EPFL benchmark circuits using a commercial 65nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow, and how simultaneously a significant improvement in PPA metrics is achieved

Anomalous Piezo-Dielectricity Of A Polymer-Derived Amorphous Silicoaluminum Oxycarbide (Sialco)

The piezo-dielectricity of a polymer-derived amorphous silicoaluminum oxycarbide (a-SiAlCO) was studied. The material showed a relatively high dielectric constant and anomalous piezo-dielectricity characterized by a positive pressure coefficient as high as 0.10–0.25 MPa−1. Further analyses indicated that this anomalous piezo-dielectricity resulted from an increase of polarizability with pressure. This phenomenon was ascribed to the unique self-formed bi-phasic (i.e., low-conductive ceramic and high-conductive free-carbon phases) structure of the SiAlCO material. The huge piezo-dielectric coefficient makes this material a very promising candidate for high-temperature sensing applications

Electric Conductivity And Microstructure Evolution Of Polymer-Derived Sialco Ceramics

The electric conductivity and microstructure of polymer-derived SiAlCO ceramic were studied. The conductivity increased drastically with increasing pyrolysis temperature and exhibited a typical Arrhenius dependence on pyrolysis temperature with the activation energy of ~7.15 eV. The microstructure was analyzed by XRD, Raman spectroscopy and XPS. Unlike previous reported PDCs, the increase in the conductivity of the SiAlCO cannot be explained by the structural changes of the free carbon phase. It is speculated that the increased conductivity is possibly due to the redistribution of C-O bonds within the free carbon phase

Impedance Spectroscopy Study On Polymer-Derived Amorphous Sialco

The electric behaviors of both free-carbon phase and ceramic phase in polymer-derived amorphous silicoaluminum oxycarbide were studied by impedance spectroscopy. The results revealed that the resistance of both ceramic phase and free-carbon phase are similar to each other and decreased with pyrolysis temperature. Meanwhile, the ceramic phase showed higher capacitance than the free-carbon phase. With increasing pyrolysis temperature, the capacitance of the ceramic phase drastically decreased, but that of the free-carbon phase remained similar. Each phase exhibited a relaxation process, which moved to higher frequency with increasing pyrolysis temperature. The results are correlated with the structural evolution of the two phases

Multi-objective Digital Design Optimisation via Improved Drive Granularity Standard Cells

To tackle the complexity of state-of-the-art electronic systems, silicon foundries continuously shrink the technology nodes and electronic design automation (EDA) vendors offer hierarchical design flows to decompose systems into smaller blocks. However, such a staged design methodology consists of various levels of abstraction, where margins will be accumulated and result in degradation of the overall design quality. This limits the full use of capabilities of both the process technology and EDA tools. In this work, a study of drive granularity of standard cells is performed and an interpolation method is proposed for drive option expansion within original cell libraries. These aim to investigate how industrial synthesis tools deal with the drive strength selection using different granularity sets. In addition, a fully-automated, multi-objective (MO) EDA digital flow is introduced for power, performance, area (PPA) optimisation based on drive strength refinement. This population-based search method better handles the increased difficulty of cell selection when using larger logic libraries, producing better optimised solutions than standard tool flow in this case. The achieved experimental results demonstrate how the improved drive granularity cells overall enhance the quality of designs and how a significant improvement in trading off PPA is achieved by the MOEDA flow

Effect Of Pyrolysis Temperature On The Electric Conductivity Of Polymer-Derived Silicoboron Carbonitride

The electric conductivity of polymer-derived SiBCNs pyrolyzed at different temperatures was studied. We showed that the boron impeded the graphitization of the free-carbon phase in the SiBCN, leading to a higher characteristic temperature and activation energy as compared to the SiCN. Such an impeding effect is due to the interaction between h-BN and graphite phase. We also provided a credible evidence to show that the increase in the electric conductivity of the SiBCN with pyrolysis temperature is likely due to the increase in the conductivity of the free-carbon phase. © 2014 Elsevier Ltd